The present invention relates to the field of computer systems. More particularly, the present invention relates to the field of memory control for computer systems.
The performance of a typical computer system is dependent on memory bandwidth, the speed at which a processor can access memory. The performance of mobile computer systems, however, is also dependent on power consumption which determines battery life. One common type of memory used in computer systems is synchronous data random access memory (SDRAM). The speed of SDRAM has increased substantially with the development of double data rate (DDR) SDRAM, which increases memory bandwidth by exchanging data on both rising and falling edges of a clock signal.
Because DDR SDRAM devices exchange data on both rising and falling edges of a clock signal, the frequency of signals on the interface lines has increased. As signal frequency increases, the likelihood of problems due to ringing and reflections on interface lines increases. As an example, reflections of a signal on a data line may result in erroneous data read from or written to a memory device. To ensure noise immunity and signal integrity on interface lines, DDR SDRAM devices utilize a terminated bus interface, called stub series terminated logic (SSTL).
DDR SDRAM devices are capable of being placed in a low power state by de-asserting a clock enable (CKE) signal to the devices. When the CKE signal is de-asserted, the devices draw less current, in part, by disabling input buffers for input signals except CKE and clock signals. In an effort to reduce power consumption, some mobile systems that use DDR SDRAM devices place the devices in a low power state when they are not accessed for a certain amount of time, thereby disabling input buffers for the devices. However, power is still consumed by the memory controller while a direct current (DC) voltage value is maintained on their inputs, due to termination requirements of SSTL. Because the DC voltage value on their inputs is not important when the input buffers are disabled, power consumed by the memory controller and termination resistors to maintain a valid DC voltage value is wasted.